1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming a semiconductor device with low-k spacers and various semiconductor devices incorporating such low-k spacers.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that substantially determines performance of such integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, whether an NFET or a PFET device, is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, a gate insulation layer and a gate electrode positioned above the gate insulation layer over the channel region. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
For many early device technology generations, the gate structures of most transistor elements has been comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-20 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. FIGS. 1A-1D depict one illustrative prior art method for forming an HK/MG replacement gate structure using a gate last technique. As shown in FIG. 1A, the process includes the formation of a basic transistor structure 200 above a semiconducting substrate 210 in an active area defined by a shallow trench isolation structure 211. At the point of fabrication depicted in FIG. 1A, the device 200 includes a sacrificial gate insulation layer 212, a dummy or sacrificial gate electrode 214, sidewall spacers 216, a layer of insulating material 217 and source/drain regions 218 formed in the substrate 210. The various components and structures of the device 200 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 212 may be comprised of silicon dioxide, the sacrificial gate electrode 214 may be comprised of polysilicon, the sidewall spacers 216 may be comprised of silicon nitride and the layer of insulating material 217 may be comprised of silicon dioxide. The source/drain regions 218 may be comprised of implanted dopant materials (N-type dopants for NFET devices and P-type dopants for PFET devices) that are implanted into the substrate 210 using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 200 that are not depicted in the drawings for purposes of clarity. For example, so-called halo implant regions are not depicted in the drawings, as well as various layers or regions of silicon/germanium that are typically found in high performance PFET transistors. At the point of fabrication depicted in FIG. 1A, the various structures of the device 200 have been formed and a chemical mechanical polishing process (CMP) has been performed to remove any materials above the sacrificial gate electrode 214 (such as a protective cap layer (not shown) comprised of silicon nitride) so that at least the sacrificial gate electrode 214 may be removed.
As shown in FIG. 1B, one or more etching processes are performed to remove the sacrificial gate electrode 214 and the sacrificial gate insulation layer 212 to thereby define a gate cavity 220 where a replacement gate structure will subsequently be formed. A masking layer that is typically used in such etching processes is not depicted for purposes of clarity. Typically, the sacrificial gate insulation layer 212 is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 212 may not be removed in all applications.
Next, as shown in FIG. 1C, various layers of material that will constitute a replacement gate structure 230 are formed in the gate cavity 220. The materials used for such replacement gate structures 230 may vary depending upon the particular application. Even in cases where the sacrificial gate insulation layer 212 is intentionally removed, there will typically be a very thin native oxide layer (not shown) that forms on the substrate 210 within the gate cavity 220. In one illustrative example, the replacement gate structure 230 is comprised of a high-k gate insulation layer 230A, such as hafnium oxide, having a thickness of approximately 2 nm, a first metal layer 230B (e.g., a layer of titanium nitride with a thickness of about 1-2 nm), a second metal layer 230C (e.g., a layer of tantalum nitride with a thickness of about 1-2 nm), a third metal layer 230D (e.g., a layer of titanium nitride with a thickness of about 5 nm) and a bulk metal layer 230E, such as aluminum. Ultimately, as shown in FIG. 1D, one or more CMP processes are performed to remove excess portions of the gate insulation layer 230A, the first metal layer 230B, the second metal layer 230C, the third metal layer 230D and the bulk metal layer 230E positioned outside of the gate cavity 220 to thereby define the replacement gate structure 230.
As device dimensions have decreased and packing densities have increased, parasitic capacitance is becoming more important as a factor to consider to improve the operating speed of transistor devices. Typically, as noted above, the gate structure of a transistor will include at least one sidewall spacer positioned adjacent the gate structure. Typically, the sidewall spacers are made of silicon nitride and they are normally formed very soon after the final gate structure is formed using a “gate-first” manufacturing technique or after the sacrificial gate structure is formed for devices manufactured using the replacement gate technique. One of the primary purposes of the silicon nitride spacers for “gate-first” devices is to protect the gate materials during subsequent processing operations. For “replacement gate” devices, the spacers also serve to protect the replacement gate structure and to define the gate cavity in the replacement gate manufacturing process.
Unfortunately, the k-value of silicon nitride is relatively high, e.g., about 7-8. The presence of the silicon nitride spacer material (with a relatively high k-value) tends to increase the parasitic capacitance between the conductive gate electrode and conductive contacts (like trench silicide regions) that are formed in close proximity to the gate structure of the transistor. This problem has become even more problematic as packing densities have increased which causes the gate structures of adjacent transistor to be positioned ever closer to one another. The use of so-called self-aligned contacts has also exacerbated this problem.
The use of alternative materials for the sidewall spacers, such as materials having k values less than about 6 or so, has been problematic. Most of such low-k materials are based upon carbon or boron doped silicon nitride. The low-k material, when used as a traditional spacer material, is subjected to a reactive ion etching (RIE) process to define the spacer from such a low-k material. The RIE process tends to deplete the carbon and boron, thereby effectively increasing the k-value of the low-k material. Such low-k materials also tend to be weaker mechanically than silicon nitride, which makes them less capable of standing up to the rigors of processing after they are formed. Moreover, such spacers are typically subjected to relatively high temperature source/drain anneal processes, which also tends to deplete the carbon and boron from such low-k materials.
The present disclosure is directed to various methods of forming a semiconductor device with low-k spacers and various semiconductor devices incorporating such low-k spacers that may solve or reduce one or more of the problems identified above.